The present invention relates to a semiconductor device and a fabrication method thereof, and particularly to a semiconductor device in which at least two field effect transistors having different threshold voltages are formed on a common base, and a fabrication method thereof.
In moving object communication systems such as portable telephones, radio waves in a range from a micro-waveband to a millimeter-waveband are utilized for transmission and receipt of audio and image data. At present, to amplify, switch and mix such high-frequency signals for transmission and receipt thereof, field effect transistors (FETs) such as Schottky metal-semiconductor field effect transistors (MESFETs) or junction field effect transistors (JFETS) formed on compound semiconductors are often used. In particular, modulation-doped FETs (MODFETs), which are advantageous in that gains can be ensured even for higher-frequency signals; the noise power of the device is low from the structural viewpoint; a high efficiency can be obtained in the case where the device is configured as a power amplifier; and the insertion loss can be lowered in the case where the device is configured as a switch, are extensively available for monolithic microwave integrated circuits (MMICs).
The MMIC using such a MODFET is expected to contain a logic circuit of a direct coupled FET logic (DCFL) type which is relatively low in power consumption. This logic circuit is required to form a decoder contained, for example, in a SPnT (n: integer) switch.
The DCFL circuit requires an enhancement FET (EFET); however, the above-described power amplifier is configured mainly by using a depletion FET (DFET). As a result, for the MMIC containing the above logic circuit, it is required to form a DFET and an EFET on the same base.
A method of forming a DFET and an EFET each of which is of the modulation-doped type on the same base is disclosed, for example, in U.S. Pat. No. 4,615,102. FIG. 5 shows a schematic sectional view of a semiconductor device which is formed in accordance with the method disclosed in the above document. Referring to FIG. 5, a channel layer 2 made from undoped GaAs, an electron supply layer 3 made from n-type AlGaAs, a threshold value control layer 4 made from n-type GaAs, a first etching stopping layer 5 made from n-type AlGaAs, a first ohmic contact layer 6 made from n-type GaAs, a second etching stopping layer 7 made from n-type AlGaAs, and a second ohmic contact layer 8 made from n-type GaAs are sequentially formed by epitaxial growth on a base 1 made from a semi-insulating GaAs, to form a stacked semiconductor layer. Then, a DFET formation area and an EFET formation area are isolated from each other, typically, by forming a trench therebetween in such a manner that the trench extends across the stacked semiconductor layer. A portion, present in the EFET formation area, of the second ohmic contact layer 8 is removed. Recesses 9R and 10R different in depth are formed in gate formation portions of the DFET and EFET formation areas, and Schottky gate electrodes 9 and 10 are formed in the recesses 9R and 10R, respectively. Source/Drain electrodes (hereinafter, referred to as "S/D electrodes") 11 and 12, and 13 and 14 are formed on both sides of the gate electrode 9 and on both sides of the gate electrode 10, respectively in such a manner as to be ohmic-contact therewith.
With this configuration, a distance between the gate electrode 9 and the channel layer 2 is different from a distance between the gate electrode 10 and the channel layer 2. In this way, a DFET and an EFET having specific threshold voltages V.sub.th different from each other can be obtained.
To accurately control a difference in threshold voltage V.sub.th between the DFET and EFET, it is required to accurately control a difference in depth between the recesses 9R and 10R in which the gate electrodes 9 and 10 are formed, and hence to accurately select the thickness of the threshold value control layer 4 and highly accurately control the depth of the recess 9R depending on the first etching stopping layer 5 and the depth of the recess 10R depending on the first and second etching stopping layer 5 and 7.
The DFET formed by the above method, however, is configured such that a drain current flows across the first and second etching stopping layers 5 and 7, that is, across the etching layers of the number corresponding to the number (two in this example) of the FETs having different threshold voltages, and consequently, such a DFET is disadvantageous in that a series resistance depending on the potential barriers of these etching stopping layers 5 and 7 or depending on the thicknesses and carrier concentrations of these etching stopping layers 5 and 7 may particularly degrade the on-resistance and transmission gain which are characteristic of the DFET.
Accordingly, the mixed arrangement of the EFET and DFET on the same substrate is achieved at large expense of the characteristic of one FET, the DFET in the example of the related art described above.
The semiconductor device including the FETs of the number corresponding to the desired number (two in the above example) of different threshold voltages is also disadvantageous in that since the etching stopping layers of the corresponding number (two in the example) are provided, the substrate structure is complicated and thereby the fabrication cost is raised.
To avoid such a disadvantage, it may be considered to eliminate all or at least one of the above-described two etching stopping layers; however, in this case, there occurs a problem in control of the depths of the gates of both the FETs.
The semiconductor device configured as the semiconductor integrated circuit device provided with the DFET and EFET each of which is of the modulation-doped type using a Schottky gate is further disadvantageous in reliability due to the known inconvenience of Schottky junction in which a Schottky electrode material is diffused onto the substrate side under a high temperature bias condition, to degrade the rectifying characteristic.